View MC74HC4053ADR2G_8663861.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2016 march, 2016 ? rev. 8 1 publication order number: mc74hc4051a/d mc74hc4051a, mc74hc4052a, mc74hc4053a analog multiplexers/ demultiplexers high?performance silicon?gate cmos the mc74hc4051a, mc74hc4052a and mc74hc4053a utilize silicon?gate cmos technology to achieve fast propagation delays, low on resistances, and low off leakage currents. these analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from v cc to v ee ). the hc4051a, hc4052a and hc4053a are identical in pinout to the metal?gate mc14051ab, mc14052ab and mc14053ab. the channel?select inputs determine which one of the analog inputs/outputs is to be connected, by means of an analog switch, to the common output/input. when the enable pin is high, all analog switches are turned off. the channel?select and enable inputs are compatible with standard cmos outputs; with pullup resistors they are compatible with lsttl outputs. these devices have been designed so that the on resistance (r on ) is more linear over input voltage than r on of metal?gate cmos analog switches. for a multiplexer/demultiplexer with injection current protection, see hc4851a and hc4852a. features ? fast switching and propagation speeds ? low crosstalk between switches ? diode protection on all inputs/outputs ? analog power supply range (v cc ? v ee ) = 2.0 to 12.0 v ? digital (control) power supply range (v cc ? gnd) = 2.0 to 6.0 v ? improved linearity and lower on resistance than metal?gate counterparts ? low noise ? in compliance with the requirements of jedec standard no. 7a ? chip complexity: hc4051a ? 184 fets or 46 equivalent gates hc4052a ? 168 fets or 42 equivalent gates hc4053a ? 156 fets or 39 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr?free and are rohs compliant this document contains information on some products that are still under development. on semiconductor reserves the right to change or discontinue these products without notice. www. onsemi.com marking diagrams soic?16 tssop?16 1 16 hc405xag awlyww hc40 5xa alyw 1 16 soic?16 wide 1 16 hc405xa awlywwg see detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. ordering information x = 1, 2 or 3 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package (note: microdot may be in either location) soic?16 d suffix case 751b tssop?16 dt suffix case 948f soic?16 wide dw suffix case 751g 4051 alyw qfn16 1 qfn16 mn suffix case 485aw
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 2 logic diagram mc74hc4051a single?pole, 8?position plus common off x0 13 x1 14 x2 15 x3 12 x4 1 x5 5 x6 2 x7 4 a 11 b 10 c 9 enable 6 multiplexer/ demultiplexer x 3 analog inputs/ channel inputs pin 16 = v cc pin 7 = v ee pin 8 = gnd common output/ input 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 x2 x1 x0 x3 a b c x4 x6 x x7 x5 enable v ee gnd pinout: mc74hc4051a (top view) outputs select l l l l h h h h x l l h h l l h h x l h l h l h l h x function table ? mc74hc4051a control inputs on channels enable select cba x0 x1 x2 x3 x4 x5 x6 x7 none l l l l l l l l h x = don?t care logic diagram mc74hc4052a double?pole, 4?position plus common off x0 12 x1 14 x2 15 x3 11 y0 1 y1 5 y2 2 y3 4 a 10 b 9 enable 6 x switch y switch x 13 analog inputs/outputs channel\select inputs pin 16 = v cc pin 7 = v ee pin 8 = gnd common outputs/inputs l l h h x l h l h x function table ? mc74hc4052a control inputs on channels enable select ba x0 x1 x2 x3 l l l l h x = don?t care pinout: mc74hc4052a (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 x2 x1 x x0 x3 a b y0 y2 y y3 y1 enable v ee gnd y 3 y0 y1 y2 y3 none
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 3 logic diagram mc74hc4053a triple single?pole, double?position plus common off x0 12 x1 13 a 11 b 10 c 9 enable 6 x switch y switch x 14 analog inputs/outputs channel\select inputs pin 16 = v cc pin 7 = v ee pin 8 = gnd common outputs/inputs l l l l h h h h x l l h h l l h h x l h l h l h l h x function table ? mc74hc4053a control inputs on channels enable select cba l l l l l l l l h x = don?t care pinout: mc74hc4053a (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 y x x1 x0 a b c y1 y0 z1 z z0 enable v ee gnd z0 z0 z0 z0 z1 z1 z1 z1 y0 y0 y1 y1 y0 y0 y1 y1 x0 x1 x0 x1 x0 x1 x0 x1 none y0 2 y1 1 y 15 z0 5 z1 3 z 4 z switch note: this device allows independent control of each switch. channel?select input a controls the x?switch, input b controls the y?switch and input c controls the z?switch maximum ratings symbol parameter value unit v cc positive dc supply voltage (referenced to gnd) (referenced to v ee ) ?0.5 to +7.0 ?0.5 to +14.0 v v ee negative dc supply voltage (referenced to gnd) ?7.0 to +5.0 v v is analog input voltage v ee ? 0.5 to v cc + 0.5 v v in digital input voltage (referenced to gnd) ?0.5 to v cc + 0.5 v i dc current, into or out of any pin 25 ma p d power dissipation in still air, soic package? tssop package? 500 450 mw t stg storage temperature range ?65 to +150 c t l lead temperature, 1 mm from case for 10 seconds soic or tssop package 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating: soic package: ?7 mw/ c from 65 to 125 c tssop package: ?6.1 mw/ c from 65 to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 4 recommended operating conditions symbol parameter min max unit v cc positive dc supply voltage (referenced to gnd) (referenced to v ee ) 2.0 2.0 6.0 12.0 v v ee negative dc supply voltage, output (referenced to gnd) ?6.0 gnd v v is analog input voltage v ee v cc v v in digital input voltage (referenced to gnd) gnd v cc v v io * static or dynamic voltage across switch 1.2 v t a operating temperature range, all package types ?55 +125 c t r , t f input rise/fall time v cc = 2.0 v (channel select or enable inputs) v cc = 3.0 v v cc = 4.5 v v cc = 6.0 v 0 0 0 0 1000 600 500 400 ns functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. *for voltage drops across switch greater than 1.2 v (switch on), excessive v cc current may be drawn; i.e., the current out of the switch may contain both v cc and switch input components. the reliability of the device will be unaffected unless the maximum ratings are exceeded. dc characteristics ? digital section (voltages referenced to gnd) v ee = gnd, except where noted symbo l parameter condition v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c v ih minimum high?level input voltage, channel?select or enable inputs r on = per spec 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum low?level input voltage, channel?select or enable inputs r on = per spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v i in maximum input leakage current, channel?select or enable inputs v in = v cc or gnd, v ee = ? 6.0 v 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) channel select, enable and v is = v cc or gnd; v ee = gnd v io = 0 v v ee = ? 6.0 6.0 6.0 1 4 10 40 20 80 a
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 5 dc characteristics ? analog section symbo l parameter condition v cc v ee guaranteed limit unit ?55 to 25 c 85 c 125 c r on maximum ?on? resistance v in = v il or v ih ; v is = v cc to v ee ; i s 2.0 ma (figures 1, 2) 4.5 4.5 6.0 0.0 ? 4.5 ? 6.0 190 120 100 240 150 125 280 170 140 v in = v il or v ih ; v is = v cc or v ee (endpoints); i s 2.0 ma (figures 1, 2) 4.5 4.5 6.0 0.0 ? 4.5 ? 6.0 150 100 80 190 125 100 230 140 115 r on maximum difference in ?on? resistance between any two channels in the same package v in = v il or v ih ; v is = 1/2 (v cc ? v ee ); i s 2.0 ma 4.5 4.5 6.0 0.0 ? 4.5 ? 6.0 30 12 10 35 15 12 40 18 14 i off maximum off?channel leakage current, any one channel v in = v il or v ih ; v io = v cc ? v ee ; switch off (figure 3) 6.0 ? 6.0 0.1 0.5 1.0 a maximum of f?channel hc4051a leakage current, hc4052a common channel hc4053a v in = v il or v ih ; v io = v cc ? v ee ; switch off (figure 4) 6.0 6.0 6.0 ? 6.0 ? 6.0 ? 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 i on maximum on?channelhc4051a leakage current, hc4052a channel?to?channel hc4053a v in = v il or v ih ; switch?to?switch = v cc ? v ee ; (figure 5) 6.0 6.0 6.0 ? 6.0 ? 6.0 ? 6.0 0.2 0.1 0.1 2.0 1.0 1.0 4.0 2.0 2.0 a ac characteristics (c l = 50 pf, input t r = t f = 6 ns) symbo l parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c t plh , t phl maximum propagation delay, channel?select to analog output (figure 9) 2.0 3.0 4.5 6.0 270 90 59 45 320 110 79 65 350 125 85 75 ns t plh , t phl maximum propagation delay, analog input to analog output (figure 10) 2.0 3.0 4.5 6.0 40 25 12 10 60 30 15 13 70 32 18 15 ns t plz , t phz maximum propagation delay, enable to analog output (figure 11) 2.0 3.0 4.5 6.0 160 70 48 39 200 95 63 55 220 110 76 63 ns t pzl , t pzh maximum propagation delay, enable to analog output (figure 11) 2.0 3.0 4.5 6.0 245 115 49 39 315 145 69 58 345 155 83 67 ns c in maximum input capacitance, channel?select or enable inputs 10 10 10 pf c i/o maximum capacitance analog i/o 35 35 35 pf (all switches off) common o/i: hc4051a hc4052a hc4053a 130 80 50 130 80 50 130 80 50 feed?through 1.0 1.0 1.0 c pd power dissipation capacitance (figure 13)* hc4051a hc4052a hc4053a typical @ 25 c, v cc = 5.0 v, v ee = 0 v pf 45 80 45 * used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 6 additional application characteristics (gnd = 0 v) symbo l parameter condition v cc v v ee v limit* unit 25 c bw maximum on?channel bandwidth or minimum frequency response (figure 6) f in = 1mhz sine wave; adjust f in voltage to obtain 0dbm at v os ; increase f in frequency until db meter reads ?3db; r l = 50 , c l = 10pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?51 ?52 ?53 mhz 80 80 80 95 95 95 120 120 120 ? off?channel feed?through isolation (figure 7) f in = sine wave; adjust f in voltage to obtain 0dbm at v is f in = 10khz, r l = 600 , c l = 50pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?50 ?50 ?50 db f in = 1.0mhz, r l = 50 , c l = 10pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?40 ?40 ?40 ? feedthrough noise. channel?select input to common i/o (figure 8) v in 1mhz square wave (t r = t f = 6ns); adjust r l at setup so that i s = 0a; enable = gnd r l = 600 , c l = 50pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 25 105 135 mv pp r l = 10k , c l = 10pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 35 145 190 ? crosstalk between any two switches (figure 12) (test does not apply to hc4051a) f in = sine wave; adjust f in voltage to obtain 0dbm at v is f in = 10khz, r l = 600 , c l = 50pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?50 ?50 ?50 db f in = 1.0mhz, r l = 50 , c l = 10pf 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 ?60 ?60 ?60 thd total harmonic distortion (figure 14) f in = 1khz, r l = 10k , c l = 50pf thd = thd measured ? thd source v is = 4.0v pp sine wave v is = 8.0v pp sine wave v is = 11.0v pp sine wave 2.25 4.50 6.00 ?2.25 ?4.50 ?6.00 0.10 0.08 0.05 % *limits not tested. determined by design and verified by qualification. figure 1a. typical on resistance, v cc ? v ee = 2.0 v figure 1b. typical on resistance, v cc ? v ee = 3.0 v 250 200 150 100 50 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 100 80 60 40 20 0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.25 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 25 c -55 c 125 c 25 c -55 c 125 c 2.0 0 300 180 160 140 120 0 2.5 2.75 3.0
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 7 figure 1c. typical on resistance, v cc ? v ee = 4.5 v figure 1d. typical on resistance, v cc ? v ee = 6.0 v 120 100 80 60 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 75 60 45 30 15 0 1.0 2.0 3.0 4.0 5.0 6.0 3.5 4.5 5.5 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 20 0 25 c -55 c 125 c 25 c -55 c 125 c 90 105 0 0.5 1.5 2.5 figure 1e. typical on resistance, v cc ? v ee = 9.0 v 01 70 60 50 40 30 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 20 10 234 56789 25 c -55 c 125 c 80 0 figure 1f. typical on resistance, v cc ? v ee = 12.0 v 01 60 50 40 30 v is , input voltage (volts), referenced to v ee r on , on resistance (ohms) 20 10 234 89101112 25 c -55 c 125 c 0 5 7 6 figure 2. on resistance test set?up plotter mini computer programmable power supply dc analyzer v cc device under test + - v ee analog in common out gnd
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 8 figure 3. maximum off channel leakage current, any one channel, test set?up figure 4. maximum off channel leakage current, common channel, test set?up figure 5. maximum on channel leakage current, channel to channel, test set?up figure 6. maximum on channel bandwidth, test set?up figure 7. off channel feedthrough isolation, test set?up figure 8. feedthrough noise, channel select to common out, test set?up off off 6 7 8 16 common o/i v cc v ee v ih nc a v cc v ee v cc off off 6 7 8 16 common o/i v cc v ee v ih analog i/o v cc v ee v cc on off 6 7 8 16 common o/i v cc v ee v il v cc v ee v cc n/c a analog i/o on 6 7 8 16 v cc v ee 0.1 f c l * f in r l db meter *includes all probe and jig capacitance off 6 7 8 16 v cc v ee 0.1 f c l * f in r l db meter *includes all probe and jig capacitance v os v os r l v is v il or v ih channel select on/off 6 7 8 16 v cc v ee c l * r l *includes all probe and jig capacitance channel select test point common o/i 11 v cc off/on analog i/o r l r l v cc gnd v in 1 mhz t r = t f = 6 ns
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 9 figure 9a. propagation delays, channel select to analog out figure 9b. propagation delay, test set?up channel select to analog out figure 10a. propagation delays, analog in to analog out figure 10b. propagation delay, test set?up analog in to analog out figure 11a. propagation delays, enable to analog out figure 11b. propagation delay, test set?up enable to analog out v cc gnd channel select analog out 50% t plh t phl 50% on/off 6 7 8 16 v cc c l * *includes all probe and jig capacitance channel select test point common o/i off/on analog i/o v cc v cc gnd analog in analog out 50% t plh t phl 50% on 6 7 8 16 v cc c l * *includes all probe and jig capacitance test point common o/i analog i/o on/off 6 7 8 enable v cc enable 90% 50% 10% t f t r v cc gnd analog out t pzl analog out t pzh high impedance v ol v oh high impedance 10% 90% t plz t phz 50% 50% analog i/o c l * test point 16 v cc 1k 1 2 1 2 position 1 when testing t phz and t pzh position 2 when testing t plz and t pzl
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 10 r l figure 12. crosstalk between any two switches, test set?up figure 13. power dissipation capacitance, test set?up figure 14a. total harmonic distortion, test set?up figure 14b. plot, harmonic distortion 0 -10 -20 -30 -40 -50 - 100 1.0 2.0 3.125 frequency (khz) db -60 -70 -80 -90 fundamental frequency device source on 6 7 8 16 v ee c l * *includes all probe and jig capacitance off r l r l v is r l c l * v os f in 0.1 f on/off 6 7 8 16 v cc channel select nc common o/i off/on analog i/o v cc a 11 v cc v ee on 6 7 8 16 v cc v ee 0.1 f c l * f in r l to distortion meter *includes all probe and jig capacitance v os v is applications information the channel select and enable control pins should be at v cc or gnd logic levels. v cc being recognized as a logic high and gnd being recognized as a logic low. in this example: v cc = +5v = logic high gnd = 0v = logic low the maximum analog voltage swings are determined by the supply voltages v cc and v ee . the positive peak analog voltage should not exceed v cc . similarly, the negative peak analog voltage should not go below v ee . in this example, the difference between v cc and v ee is ten volts. therefore, using the configuration of figure 15, a maximum analog signal of ten volts peak?to?peak can be controlled. unused analog inputs/outputs may be left floating (i.e., not connected). however, tying unused analog inputs and outputs to v cc or gnd through a low value resistor helps minimize crosstalk and feed?through noise that may be picked up by an unused switch. although used here, balanced supplies are not a requirement. the only constraints on the power supplies are that: v cc ? gnd = 2 to 6 volts v ee ? gnd = 0 to ?6 volts v cc ? v ee = 2 to 12 volts and v ee gnd when voltage transients above v cc and/or below v ee are anticipated on the analog channels, external germanium or schottky diodes (d x ) are recommended as shown in figure 16. these diodes should be able to absorb the maximum anticipated current surges during clipping.
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 11 analog signal figure 15. application example figure 16. external germanium or schottky clipping diodes a. using pull?up resistors b. using hct interface figure 17. interfacing lsttl/nmos to cmos inputs on 6 7 8 16 +5v -5v analog signal +5v -5v +5v -5v 11 10 9 to external cmos circuitry 0 to 5v digital signals on/off 7 8 16 v cc v ee v ee d x v cc d x v ee d x v cc d x analog signal on/off 6 7 8 16 +5v v ee analog signal +5v v ee +5v v ee 11 10 9 r * r r lsttl/nmos circuitry +5v * 2k r 10k analog signal on/off 6 7 8 16 +5v v ee analog signal +5v v ee +5v v ee 11 10 9 lsttl/nmos circuitry +5v hct buffer figure 18. function diagram, hc4051a 13 x0 14 x1 15 x2 12 x3 1 x4 5 x5 2 x6 4 x7 3 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 12 figure 20. function diagram, hc4053a figure 19. function diagram, hc4052a 13 x1 12 x0 1 y1 2 y0 3 z1 5 z0 14 x level shifter level shifter level shifter level shifter 11 a 10 b 9 c 6 enable 12 x0 14 x1 15 x2 11 x3 1 y0 5 y1 2 y2 4 y3 3 y level shifter level shifter level shifter 10 a 9 b 6 enable 13 x 15 y 4 z
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 13 ordering information device package shipping ? mc74hc4051adg soic?16 (pb?free) 48 units / rail mc74hc4051adr2g 2500 units / tape & reel nlv74hc4051adr2g* 2500 units / tape & reel mc74hc4051adwg soic?16 wide (pb?free) 48 units / rail mc74hc4051adwr2g 1000 units / tape & reel nlvhc4051adwr2g* 1000 units / tape & reel mc74hc4051adtg tssop?16 (pb?free) 96 units / rail mc74hc4051adtr2g 2500 units / tape & reel nlvhc4051adtr2g* 2500 units / tape & reel mc74hc4052adg soic?16 (pb?free) 48 units / rail mc74hc4052adr2g 2500 units / tape & reel nlv74hc4052adr2g* 2500 units / tape & reel mc74hc4052adwg soic?16 wide (pb?free) 48 units / rail mc74hc4052adwr2g 1000 units / tape & reel mc74hc4052adtg tssop?16 (pb?free) 96 units / rail mc74hc4052adtr2g 2500 units / tape & reel nlv74hc4052adtr2g* 2500 units / tape & reel nlvhc4052adtr2g* 2500 units / tape & reel nlvhc4052amntwg* (in development) qfn16 (pb?free) 3000 units / tape & reel mc74hc4053adg soic?16 (pb?free) 48 units / rail MC74HC4053ADR2G 2500 units / tape & reel nlv74hc4053adr2g* 2500 units / tape & reel mc74hc4053adwg soic?16 wide (pb?free) 48 units / rail nlv74hc4053adwrg* 1000 units / tape & reel mc74hc4053adwr2g 1000 units / tape & reel nlv74hc4053adwr2g* 1000 units / tape & reel mc74hc4053adtg tssop?16 (pb?free) 96 units / rail mc74hc4053adtr2g 2500 units / tape & reel nlvhc4053adtr2g* 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 14 package dimensions tssop?16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 15 package dimensions soic?16 wb case 751g?03 issue d d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7 11.00 16x 0.58 16x 1.62 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 16 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch 16 89 8x
mc74hc4051a, mc74hc4052a, mc74hc4053a www. onsemi.com 17 package dimensions qfn16, 2.5x3.5, 0.5p case 485aw issue o dim min max millimeters a a1 0.00 0.05 a3 b 0.20 0.30 d 2.50 bsc d2 0.85 1.15 e 3.50 bsc e2 e 0.50 bsc k 0.20 --- notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimensions b applies to plated terminal and is measured between 0.15 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 0.20 ref b d2 l pin one e2 1 8 15 10 d e b a c 0.15 c 0.15 2x 2x e 2 16x 16x 0.10 c 0.05 c a b note 3 a 16x k a1 (a3) seating plane c 0.08 c 0.10 0.80 1.00 l 0.35 0.45 1.85 2.15 l1 detail a l alternate terminal constructions l ??? ??? *for additional information on our pb?free strategy and solderin g details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.80 3.80 1.10 0.50 0.60 16x 0.30 16x dimensions: millimeters 1 reference top view side view note 4 c 0.15 c a b 0.15 c a b detail a bottom view e/2 l1 --- 0.15 2.10 pitch package outline p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc4051a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner.

▲Up To Search▲

Price & Availability of MC74HC4053ADR2G

	To Download MC74HC4053ADR2G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .